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Super SequencerTM with Voltage Readback ADC ADM1064
FEATURES
Complete supervisory and sequencing solution for up to 10 supplies 10 supply fault detectors enable supervision of supplies to better than 1% accuracy 5 selectable input attenuators allow supervision: Supplies up to 14.4 V on VH Supplies up to 6 V on VP1-4 5 dual-function inputs, VX1-5: High impedance input to supply fault detector with thresholds between 0.573 V and 1.375 V General-purpose logic input 10 programmable output drivers (PDO1-10): Open collector with external pull-up Push/pull output, driven to VDDCAP or VPn Open collector with weak pull-up to VDDCAP or VPn Internally charge-pumped high drive for use with external N-FET (PDO1-6 only) Sequencing engine (SE) implements state machine control of PDO outputs: State changes conditional on input events Enables complex control of boards Power-up and power-down sequence control Fault event handling Interrupt generation on warnings Watchdog function can be integrated in SE Program software control of sequencing through SMBus 12-bit ADC for readback of all supervised voltages 2 auxiliary (single-ended) ADC inputs Reference input, REFIN, has 2 input options: Driven directly from 2.048V (0.25%) REFOUT pin More accurate external reference for improved ADC performance Device powered by the highest of VP1-4, VH for improved redundancy User EEPROM: 256 bytes Industry-standard 2-wire bus interface (SMBus) Guaranteed PDO low with VH, VPn = 1.2 V 40-lead 6 mm x 6 mm LFCSP and 48-lead 7 mm x 7 mm TQFP packages
FUNCTIONAL BLOCK DIAGRAM
AUX1 AUX2 REFIN REFOUT REFGND SDA SCL A1 A0
ADM1064
MUX
VREF
SMBus INTERFACE
12-BIT SAR ADC
EEPROM
VX1 VX2 VX3 VX4 VX5
DUALFUNCTION INPUTS (LOGIC INPUTS OR SFDs) SEQUENCING ENGINE
CONFIGURABLE OUTPUT DRIVERS (HV CAPABLE OF DRIVING GATES OF N-CHANNEL FET)
PDO1 PDO2 PDO3 PDO4 PDO5 PDO6
VP1 VP2 VP3 VP4 VH AGND PROGRAMMABLE RESET GENERATORS (SFDs)
CONFIGURABLE OUTPUT DRIVERS (LV CAPABLE OF DRIVING LOGIC SIGNALS)
PDO7 PDO8 PDO9 PDO10 PDOGND
VDD ARBITRATOR
VDDCAP
04633-001
GND
Figure 1.
APPLICATIONS
Central office systems Servers/routers Multivoltage system line cards DSP/FPGA supply sequencing In-circuit testing of margined supplies
GENERAL DESCRIPTION
The ADM1064 is a configurable supervisory/sequencing device that offers a single-chip solution for supply monitoring and sequencing in multiple supply systems. In addition to these functions, the ADM1064 integrates a 12-bit ADC which can be used to accurately read back up to 12 separate voltages. (continued on Page 3)
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.326.8703 (c) 2004 Analog Devices, Inc. All rights reserved.
ADM1064 TABLE OF CONTENTS
General Description ......................................................................... 3 Specifications..................................................................................... 4 Pin Configurations and Function Descriptions ........................... 7 Absolute Maximum Ratings............................................................ 8 Thermal Characteristics .............................................................. 8 ESD Caution.................................................................................. 8 Typical Performance Characteristics ............................................. 9 Powering the ADM1064 ................................................................ 12 Inputs................................................................................................ 13 Supply Supervision..................................................................... 13 Programming the Supply Fault Detectors............................... 13 Input Comparator Hysteresis.................................................... 14 Input Glitch Filtering ................................................................. 14 Supply Supervision with VXn Inputs....................................... 14 VXn Pins as Digital Inputs........................................................ 15 Outputs ............................................................................................ 16 Supply Sequencing through Configurable Output Drivers .. 16 Sequencing Engine ......................................................................... 17 Overview...................................................................................... 17 Warnings...................................................................................... 17 SMBus Jump/Unconditional Jump .......................................... 17 Sequencing Engine Application Example ............................... 18 Sequence Detector...................................................................... 19 Monitoring Fault Detector ........................................................ 19 Timeout Detector ....................................................................... 19 Fault Reporting........................................................................... 19 Voltage Readback............................................................................ 20 Supply Supervision with the ADC ........................................... 20 Applications Diagram .................................................................... 21 Communicating with the ADM1064 ........................................... 22 Configuration Download at Power-Up................................... 22 Updating the Configuration ..................................................... 22 Updating the Sequencing Engine............................................. 23 Internal Registers........................................................................ 23 EEPROM ..................................................................................... 23 Serial Bus Interface..................................................................... 23 Write Operations ........................................................................ 25 Read Operations......................................................................... 27 Outline Dimensions ....................................................................... 29 Ordering Guide .......................................................................... 29
REVISION HISTORY
10/04--Revision 0: Initial Version
Rev. 0 | Page 2 of 32
ADM1064 GENERAL DESCRIPTION
(continued from Page 1) The device also provides up to ten programmable inputs for monitoring under, over, or out-of-window faults on up to ten supplies. In addition, ten programmable outputs can be used as logic enables. Six of them can also provide up to a 12 V output for driving the gate of an N-channel FET, which can be placed in the path of a supply. The logical core of the device is a sequencing engine. This statemachine-based construction provides up to 63 different states. This design enables very flexible sequencing of the outputs, based on the condition of the inputs. The device is controlled via configuration data that can be programmed into an EEPROM. The whole configuration can be programmed using an intuitive GUI-based software package provided by ADI.
AUX2 AUX1
REFIN REFOUT REFGND SDA SCL A1
A0
ADM1064
VREF
SMBus INTERFACE
12-BIT SAR ADC
OSC DEVICE CONTROLLER EEPROM
GPI SIGNAL CONDITIONING VX1 VX2 VX3 VX4 GPI SIGNAL CONDITIONING VX5 SEQUENCING ENGINE SFD SELECTABLE ATTENUATOR SFD
CONFIGURABLE O/P DRIVER (HV)
PDO1
PDO2 PDO3 PDO4 PDO5 CONFIGURABLE O/P DRIVER (HV)
PDO6
VP1 VP2 VP3 VP4 VH
SFD
CONFIGURABLE O/P DRIVER (LV)
PDO7 PDO8 PDO9
SELECTABLE ATTENUATOR
SFD
CONFIGURABLE O/P DRIVER (LV)
PDO10 PDOGND
AGND VDDCAP VDD ARBITRATOR REG 5.25V CHARGE PUMP
GND
VCCP
Figure 2. Detailed Block Diagram
Rev. 0 | Page 3 of 32
04633-002
ADM1064 SPECIFICATIONS
VH = 3.0 V to 14.4 V1, VPn = 3.0 V to 6.0 V1, TA = -40C to +85C, unless otherwise noted. Table 1.
Parameter POWER SUPPLY ARBITRATION VH, VPn VP VH VDDCAP CVDDCAP POWER SUPPLY Supply Current, IVH, IVPn Additional Currents All PDO FET Drivers On Current Available from VDDCAP DACs Supply Current ADC Supply Current EEPROM Erase Current SUPPLY FAULT DETECTORS VH Pin Input Attenuator Error Detection Ranges High Range Midrange VPn Pins Input Attenuator Error Detection Ranges Midrange Low Range Ultralow Range VX Pins Input Impedance Detection Ranges Ultralow Range Absolute Accuracy Threshold Resolution Digital Glitch Filter ANALOG-TO-DIGITAL CONVERTER Signal Range 2.2 1 10 Min 3.0 6.0 14.4 5.4 Typ Max Unit V V V V F mA mA 2 mA mA mA mA Test Conditions/Comments Minimum supply required on one of VPn, VH Maximum VDDCAP = 5.1 V, typical VDDCAP = 4.75 V Regulated LDO output Minimum recommended decoupling capacitance VDDCAP = 4.75 V, PDO1-10 off, DACs off, ADC off VDDCAP = 4.75 V, PDO1-6 loaded with 1 A each, PDO7-10 off Maximum additional load that can be drawn from all PDO pull-ups to VDDCAP 6 DACs on with 100 A maximum load on each Running round-robin loop 1 ms duration only, VDDCAP = 3 V
2.7 10
4.75
4.2 1
6
0.05 6 2.5 0.05 2.5 1.25 0.573 1 0.573 1.375 1 8 0 100 0 VREFIN 6 3 1.375 14.4 6
% V V % V V V M V % Bits s s V
Midrange and high range
Low range and midrange
No input attenuation error
No input attenuation error VREF error + DAC nonlinearity + comparator offset error + input attenuation error Minimum programmable filter length Maximum programmable filter length The ADC can convert signals presented to the VH, VPn, and VX_GPIn pins. VPn and VH input signals are attenuated depending on selected range. A signal at the pin corresponding to the selected range is from 0.573 V to 1.375 V at the ADC input.
Rev. 0 | Page 4 of 32
ADM1064
Parameter Input Reference Voltage on REFIN Pin, VREFIN Resolution INL Gain Error Conversion Time Offset Error Input Noise REFERENCE OUTPUT Reference Output Voltage Load Regulation Minimum Load Capacitance Load Regulation PSRR PROGRAMMABLE DRIVER OUTPUTS High Voltage (Charge Pump) Mode (PDO1-6) Output Impedance VOH IOUTAVG Standard (Digital Output) Mode (PDO1-10) VOH Min Typ 2.048 12 2.5 0.05 0.44 84 2 0.25 2.043 2.048 -0.25 0.25 2 60 2.053 Max Unit V Bits LSB % ms ms LSB LSBrms V mV mV F mV dB Test Conditions/Comments
Endpoint corrected, VREFIN = 2.048 V VREFIN = 2.048 V One conversion on one channel All 12 channels selected, 16x averaging enabled VREFIN = 2.048 V Direct input (no attenuator) No load Sourcing current, IDACnMAX = -100 A Sinking current, IDACnMAX = 100 A Capacitor required for decoupling, stability Per 100 A DC
1
11 10.5
500 12.5 12 20
14 13.5
k V V A V V V V mA mA k mA
IOH = 0 IOH = 1A 2 V < VOH < 7 V VPU (pull-up to VDDCAP or VPN) = 2.7 V, IOH = 0.5 mA VPU to Vpn = 6.0 V, IOH = 0 mA VPU 2.7 V, IOH = 0.5 mA IOL = 20 mA Maximum sink current per PDO pin Maximum total sink for all PDOs Internal pull-up Current load on any VPn pull-ups, that is, total source current available through any number of PDO pull-up switches configured onto any one VPDO = 14.4 V All on-chip time delays derived from this clock Maximum VIN = 5.5 V Maximum VIN = 5.5 V VIN = 5.5 V VIN = 0 VDDCAP = 4.75, TA = 25C, if known logic state is required
2.4 4.5 VPU - 0.3 0
VOL IOL2 ISINK 2 RPULL-UP ISOURCE (VPn)2
0.50 20 60 20 2
Three-State Output Leakage Current Oscillator Frequency DIGITAL INPUTS (VXn, A0, A1) Input High Voltage, VIH Input Low Voltage, VIL Input High Current, IIH Input Low Current, IIL Input Capacitance Programmable Pull-Down Current, IPULL-DOWN SERIAL BUS DIGITAL INPUTS (SDA, SCL) Input High Voltage, VIH Input Low Voltage, VIL Output Low Voltage, VOL2
90 2.0
100
10 110
A kHz V V A A pF A
0.8 -1 1 5 20
2.0 0.8 0.4
V V V
IOUT = -3.0 mA
Rev. 0 | Page 5 of 32
ADM1064
Parameter SERIAL BUS TIMING Clock Frequency, fSCLK Bus Free Time, tBUF Start Setup Time, tSU;STA Start Hold Time, tHD;STA SCL Low Time, tLOW SCL High Time, tHIGH SCL, SDA Rise Time, tr SCL, SDA Fall Time, tf Data Setup Time, tSU;DAT Data Hold Time, tHD;DAT Input Low Current, IIL SEQUENCING ENGINE TIMING State Change Time Min Typ Max 400 4.7 4.7 4 4.7 4 1000 300 250 5 1 10 Unit kHz s s s s s s s ns ns A s Test Conditions/Comments
VIN = 0
1 2
At least one of the VH, VP1-4 pins must be 3.0 V to maintain the device supply on VDDCAP. Specification is not production tested, but is supported by characterization data at initial product release.
Rev. 0 | Page 6 of 32
ADM1064 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
PDOGND VDDCAP VCCP AUX1 AUX2 GND SDA SCL
PDOGND
38
VDDCAP
VCCP
AUX1
AUX2
GND
SDA
SCL
NC
A1
A0
40
39
38
37
36
35
34
33
32
31 30 PDO1
48
47
46
45
44
43
42
41
40
39
37 36 NC
VX1 1 VX2 2 VX3 3 VX4 4 VX5 5 VP1 6 VP2 7 VP3 8 VP4 9 VH 10
11 12 13 14 15 16 17 18 19 20 PIN 1 INDICATOR
NC 1 VX1 2 VX2 3 VX3 4 VX4 5 VX5 6 VP1 7 VP2 8 VP3 9 VP4 10 VH 11 NC 12
13 14 15 16 17 18 19 20 21 22 23 24 PIN 1 INDICATOR
NC
35 PDO1 34 PDO2 33 PDO3 32 PDO4 31 PDO5 30 PDO6 29 PDO7 28 PDO8 27 PDO9 26 PDO10 25 NC
A1 NC
29 PDO2 28 PDO3 27 PDO4
ADM1064
TOP VIEW (Not to Scale)
26 PDO5 25 PDO6 24 PDO7 23 PDO8 22 PDO9 21 PDO10
ADM1064
TOP VIEW (Not to Scale)
REFIN
NC
NC
NC
NC
NC
AGND
REFGND
REFOUT
NC
REFIN
REFOUT
NC
NC
NC
NC
A0
NC
NC
AGND
NC = NO CONNECT
Figure 3. LFCSP Pin Configuration
Figure 4. TQFP Pin Configuration
Table 2. Pin Function Descriptions
Pin No. LFCSP TQFP 15-20 1, 12-13, 18-25, 36-37, 48 1-5 2-6 6-9 7-10 Mnemonic NC Description No connection.
VX1-5 VP1-4
10
11
VH
11 12 13 14 21-30 31 32 33 34 35 36 37 38 39 40
14 15 16 17 26-35 38 39 40 41 42 43 44 45 46 47
AGND REFGND REFIN REFOUT PDO10-1 PDOGND VCCP A0 A1 SCL SDA AUX2 AUX1 VDDCAP GND
High Impedance Inputs to Supply Fault Detectors. Fault thresholds can be set from 0.573 V to 1.375 V. Alternatively, these pins can be used as general-purpose digital inputs. Low Voltage Inputs to Supply Fault Detectors. Three input ranges can be set by altering the input attenuation on a potential divider connected to these pins, the output of which connects to a supply fault detector. These pins allow thresholds from 2.5 V to 6.0 V, 1.25 V to 3.00 V, and 0.573 V to 1.375 V. High Voltage Input to Supply Fault Detectors. Three input ranges can be set by altering the input attenuation on a potential divider connected to this pin, the output of which connects to a supply fault detector. This pin allows thresholds from 6.0 V to 14.4 V and 2.5 V to 6.0 V. Ground Return for Input Attenuators. Ground Return for On-Chip Reference Circuits. Reference Input for ADC. Nominally, 2.048 V. 2.048 V Reference Output. Programmable Output Drivers. Ground Return for Output Drivers. Central Charge-Pump Voltage of 5.25 V. A reservoir capacitor must be connected between this pin and GND. Logic Input. This pin sets the seventh bit of the SMBus interface address. Logic Input. This pin sets the sixth bit of the SMBus interface address. SMBus Clock Pin. Open-drain output requires external resistive pull-up. SMBus Data I/O Pin. Open-drain output requires external resistive pull-up. Auxiliary, Single-Ended ADC Input. Auxiliary, Single-Ended ADC Input. Device Supply Voltage. Linearly regulated from the highest of the VP1-4, VH pins to a typical of 4.75 V. Supply Ground.
Rev. 0 | Page 7 of 32
04633-004
NC = NO CONNECT
04633-003
REFGND
NC
ADM1064 ABSOLUTE MAXIMUM RATINGS
Table 3.
Parameter Voltage on VH Pin Voltage on VP Pins Voltage on VX Pins Voltage on AUX1, AUX2, REFIN Pins Input Current at Any Pin Package Input Current Maximum Junction Temperature (TJ max) Storage Temperature Range Lead Temperature, Soldering Vapor Phase, 60 s Rating 16 V 7V -0.3 V to +6.5 V -0.3 V to +5 V 5 mA 20 mA 150C -65C to +150C 215C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
THERMAL CHARACTERISTICS
40-lead LFCSP package: JA = 25C/W 48-lead TQFP package: JA = 14.8C/W
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
Rev. 0 | Page 8 of 32
ADM1064 TYPICAL PERFORMANCE CHARACTERISTICS
6
180 160
5
140
4
120
VVDDCAP (V)
IVP1 (A)
100 80 60 40
3
2
1
20 0 0 1 2 3 VVP1 (V) 4 5 6
0 0 1 2 3 VVP1 (V) 4 5 6
Figure 5. VVDDCAP vs. VVP1
Figure 8. IVP1 vs. VVP1 (VP1 Not as Supply)
6
5.0 4.5
5
4.0 3.5 3.0
4
VVDDCAP (V)
IVH (mA)
3
2.5 2.0 1.5 1.0
2
1
04633-051
0.5 0 0 2 4 6 8 VVH (V) 10 12 14 16
0 0 2 4 6 8 VVH (V) 10 12 14 16
Figure 6. VVDDCAP vs. VVH
Figure 9. IVH vs. VVH (VH as Supply)
5.0 4.5 4.0 3.5
350
300 250
IVP1 (mA)
3.0 2.5 2.0 1.5 1.0 0.5 0 0 1 2 3 VVP1 (V) 4 5 6
04633-052
IVH (A)
200 150
100
0 0 1 2 3 VVH (V) 4 5 6
Figure 7. IVP1 vs. VVP1 (VP1 as Supply)
Figure 10. IVH vs. VVH (VH Not as Supply)
Rev. 0 | Page 9 of 32
04633-055
50
04633-054
04633-053
04633-050
ADM1064
14
1.0 0.8 0.6
12
VPDO1 CHARGE PUMPED
10 8
0.4
DNL (LSB)
0.2 0 -0.2 -0.4 -0.6
6 4
04633-056
-0.8 -1.0 0 1000 2000 CODE 3000 4000
0 0 2.5 5.0 7.5 10.0 12.5 ILOAD CURRENT (A)
15.0
Figure 11. VPDO1 (FET Drive Mode) vs. ILOAD
Figure 14. DNL for ADC
5.0 4.5 4.0 3.5
1.0 0.8 0.6 0.4
VPDO1 (V)
VP1 = 5V 2.5 VP1 = 3V 2.0 1.5 1.0
04633-057
INL (LSB)
3.0
0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0 0 1000 2000 CODE 3000 4000
04633-063
0.5 0 0 1 2 3 ILOAD (mA) 4 5 6
Figure 12. VPDO1 (Strong Pull-Up VP) vs. ILOAD
Figure 15. INL for ADC
4.5 4.0
12000 9894 10000
3.5 VP1 = 5V
2.5 VP1 = 3V 2.0 1.5 1.0
HITS PER CODE
3.0
8000
VPDO1 (V)
6000
4000
2000
04633-058
0.5 0 0 10 20 30 ILOAD (A) 40 50 60
25 0 2047 2048 CODE
81 2049
Figure 13. VPDO1 (Weak Pull-Up to VP) vs. ILOAD
Figure 16. ADC Noise, Midcode Input, 10,000 Reads
Rev. 0 | Page 10 of 32
04633-064
04633-066
2
ADM1064
2.058
2.053
REFOUT (V)
VP1 = 3.0V 2.048 VP1 = 4.75V
2.043
04633-061
2.038 -40
-20
0
20
40
60
80
100
TEMPERATURE (C)
Figure 17. REFOUT vs. Temperature
Rev. 0 | Page 11 of 32
ADM1064 POWERING THE ADM1064
The ADM1064 is powered from the highest voltage input on either the positive-only supply inputs (VPn) or the high voltage supply input (VH). This technique offers improved redundancy as the device is not dependent on any particular voltage rail to keep it operational. The same pins are used for supply fault detection (discussed later in the next section). A VDD arbitrator on the device chooses which supply to use. The arbitrator can be considered an OR'ing of five LDOs together. A supply comparator chooses which of the inputs is highest and selects this one to provide the on-chip supply. There is minimal switching loss with this architecture (~0.2 V), resulting in the ability to power the ADM1064 from a supply as low as 3.0 V. Note that the supply on the VXn pins cannot be used to power the device. An external capacitor to GND is required to decouple the onchip supply from noise. This capacitor should be connected to the VDDCAP pin, as shown in Figure 18. The capacitor has another use during brownouts (momentary loss of power). Under these conditions, when the input supply (VPn or VH) dips transiently below VDD, the synchronous rectifier switch immediately turns off so that it does not pull VDD down. The VDD cap can then act as a reservoir to keep the device active until the next highest supply takes over the powering of the device. 10 F is recommended for this reservoir/decoupling function. Note that when two or more supplies are within 100 mV of each other, the supply that takes control of VDD first keeps control. For example, if VP1 is connected to a 3.3 V supply, then VDD powers up to approximately 3.1 V through VP1. If VP2 is then connected to another 3.3 V supply, VP1 still powers the device, unless VP2 goes 100 mV higher than VP1.
VDDCAP VP1 IN OUT 4.75V LDO OUT 4.75V LDO OUT 4.75V LDO OUT 4.75V LDO OUT 4.75V LDO INTERNAL DEVICE SUPPLY
EN VP2 IN EN VP3 IN EN VP4 IN EN VH IN
EN
SUPPLY COMPARATOR
04633-022
Figure 18. VDD Arbitrator Operation
Rev. 0 | Page 12 of 32
ADM1064 INPUTS
SUPPLY SUPERVISION
The ADM1064 has ten programmable inputs. Five of these are dedicated supply fault detectors (SFDs). These dedicated inputs are called VH and VP1-4 by default. The other five inputs are labeled VX1-VX5 and have dual functionality. They can be used as either supply fault detectors, with similar functionality to VH and VP1-4, or CMOS/TTL-compatible logic inputs to the devices. Therefore, the ADM1064 can have up to ten analog inputs, a minimum of five analog inputs and five digital inputs, or a combination. If an input is used as an analog input, it cannot be used as a digital input. Therefore, a configuration requiring ten analog inputs has no digital inputs available. Table 5 shows the details of each of the inputs.
RANGE SELECT ULTRA LOW VPn VREF + - OV COMPARATOR GLITCH FILTER FAULT OUTPUT
The resolution is given by Step Size = Threshold Range/255 Therefore, if the high range is selected on VH, the step size can be calculated as follows: (14.4 V - 4.8 V)/255 = 37.6 mV Table 4 lists the upper and lower limit of each available range, the bottom of each range (VB), and the range itself (VR). Table 4. Voltage Range Limits
Voltage Range (V) 0.573 to 1.375 1.25 to 3.00 2.5 to 6.0 4.8 to 14.4 VB (V) 0.573 1.25 2.5 4.8 VR (V) 0.802 1.75 3.5 9.6
The threshold value required is given by VT = (VR x N)/255 + VB
+ LOW - MID FAULT TYPE UV SELECT COMPARATOR
04633-023
where: VT is the desired threshold voltage (UV or OV). VR is the voltage range. N is the decimal value of the 8-bit code. VB is the bottom of the range. Reversing the equation, the code for a desired threshold is given by N = 255 x (VT - VB)/VR For example, if the user wants to set a 5 V OV threshold on VP1, the code to be programmed in the PS1OVTH register (discussed in the AN-698 application note) is given by N = 255 x (5 - 2.5)/3.5 Therefore, N = 182 (1011 0110 or 0xB6).
Figure 19. Supply Fault Detector Block
PROGRAMMING THE SUPPLY FAULT DETECTORS
The ADM1064 has up to ten supply fault detectors (SFDs) on its ten input channels. These highly programmable reset generators enable the supervision of up to ten supply voltages. The supplies can be as low as 0.573 V and as high as 14.4 V. The inputs can be configured to detect an undervoltage fault (the input voltage droops below a preprogrammed value), an overvoltage fault (the input voltage rises above a preprogrammed value) or an out-ofwindow fault (undervoltage or overvoltage). The thresholds can be programmed to an 8-bit resolution in registers provided in the ADM1064. This translates to a voltage resolution that is dependent on the range selected.
Table 5. Input Functions, Thresholds, and Ranges
Input VH VPn Function High V Analog Input Positive Analog Input Voltage Range (V) 2.5-6.0 4.8-14.4 0.573-1.375 1.25-3.00 2.5-6.0 0.573-1.375 0-5 Maximum Hysteresis 425 mV 1.16 V 97.5 mV 212 mV 425 mV 97.5 mV N/A Voltage Resolution (mV) 13.7 37.6 3.14 6.8 13.7 3.14 N/A Glitch Filter (s) 0-100 0-100 0-100 0-100 0-100 0-100 0-100
VXn
High Z Analog Input Digital Input
Rev. 0 | Page 13 of 32
ADM1064
INPUT COMPARATOR HYSTERESIS
The UV and OV comparators shown in Figure 19 are always looking at VPn. To avoid chattering (multiple transitions when the input is very close to the set threshold level), these comparators have digitally programmable hysteresis. The hysteresis can be programmed up to the values shown in Table 5. The hysteresis is added after a supply voltage goes out of tolerance. Therefore, the user can program how much above the UV threshold the input must rise again before a UV fault is deasserted. Similarly, the user can program how much below the OV threshold an input must fall again before an OV fault is deasserted. The hysteresis figure is given by VHYST = VR x NTHRESH/255 where: VHYST is the desired hysteresis voltage. NTHRESH is the decimal value of the 5-bit hysteresis code. Note that NTHRESH has a maximum value of 31. The maximum hysteresis for the ranges is listed in Table 5.
INPUT PULSE SHORTER THAN GLITCH FILTER TIMEOUT PROGRAMMED TIMEOUT INPUT PULSE LONGER THAN GLITCH FILTER TIMEOUT PROGRAMMED TIMEOUT
INPUT
INPUT
T0
TGF
T0
TGF
OUTPUT
OUTPUT
04633-024
T0
TGF
T0
TGF
Figure 20. Input Glitch Filter Function
SUPPLY SUPERVISION WITH VXn INPUTS
The VXn inputs have two functions. They can be used as either supply fault detectors or digital logic inputs. When selected as an analog (SFD) input, the VXn pins have very similar functionality to the VH and VPn pins. The major difference is that the VXn pins have only one input range: 0.573 V to 1.375 V. Therefore, these inputs can directly supervise only the very low supplies. However, the input impedance of the VXn pins is high, allowing an external resistor divide network to be connected to the pin. Thus, any supply can be potentially divided down into the input range of the VXn pin and supervised. This enables the ADM1064 to monitor other supplies such as +24 V, +48 V, and -5 V. An additional supply supervision function is available when the VXn pins are selected as digital inputs. In this case, the analog function is available as a second detector on each of the dedicated analog inputs, VP1-4 and VH. The analog function of VX1 is mapped to VP1, VX2 is mapped to VP2, and so on. VX5 is mapped to VH. In this case, these SFDs can be viewed as a secondary or warning SFD. The secondary SFDs are fixed to the same input range as the primary SFD. They are used to indicate warning levels rather than failure levels. This allows faults and warnings to be generated on a single supply using only one pin. For example, if VP1 is set to output a fault if a 3.3 V supply droops to 3.0 V, VX1 can be set to output a warning at 3.1 V. Warning outputs are available for readback from the status registers. They are also OR'ed together and fed into the sequencing engine (SE), allowing warnings to generate interrupts on the PDOs. Therefore, in the example above, if the supply droops to 3.1 V, a warning is generated, and remedial action can be taken before the supply drops out of tolerance.
INPUT GLITCH FILTERING
The final stage of the SFDs is a glitch filter. This block provides time-domain filtering on the output of the SFD comparators. This allows the user to remove any spurious transitions such as supply bounce at turn-on. The glitch filter function is additional to the digitally programmable hysteresis of the SFD comparators. The glitch filter timeout is programmable up to 100 s. For example, when the glitch filter timeout is 100 s, any pulses appearing on the input of the glitch filter block that are less than 100 s in duration are prevented from appearing on the output of the glitch filter block. Any input pulse that is longer than 100 s does appear on the output of the glitch filter block. The output is delayed with respect to the input by 100 s. The filtering process is shown in Figure 20.
Rev. 0 | Page 14 of 32
ADM1064
VXn PINS AS DIGITAL INPUTS
As mentioned previously, the VXn input pins on the ADM1064 have dual functionality. The second function is as a digital input to the device. Therefore, the ADM1064 can be configured for up to five digital inputs. These inputs are TTL/CMOS-compatible. Standard logic signals can be applied to the pins: RESET from reset generators, PWRGOOD signals, fault flags, manual resets, and so on. These signals are available as inputs to the SE, and can be used to control the status of the PDOs. The inputs can be configured to detect either a change in level or an edge. When configured for level detection, the output of the digital block is a buffered version of the input. When configured for edge detection, once the logic transition is detected, a pulse of programmable width is output from the digital block. The width is programmable from 0 s to 100 s. The digital blocks feature the same glitch filter function that is available on the SFDs. This enables the user to ignore spurious transitions on the inputs. For example, the filter can be used to debounce a manual reset switch. When configured as digital inputs, each of the VXn pins has a weak (10 A) pull-down current source available for placing the input in a known condition, even if left floating. The current source, if selected, weakly pulls the input to GND.
VXn (DIGITAL INPUT) + DETECTOR -
04633-027
GLITCH FILTER
TO SEQUENCING ENGINE
VREF = 1.4V
Figure 21. VXn Digital Input Function
Rev. 0 | Page 15 of 32
ADM1064 OUTPUTS
SUPPLY SEQUENCING THROUGH CONFIGURABLE OUTPUT DRIVERS
Supply sequencing is achieved with the ADM1064 using the programmable driver outputs (PDOs) on the device as control signals for supplies. The output drivers can be used as logic enables or as FET drivers. The sequence in which the PDOs are asserted (and, therefore, the supplies are turned on) is controlled by the sequencing engine (SE). The SE determines what action is to be taken with the PDOs based on the condition of the inputs of the ADM1064. Therefore, the PDOs can be set up to assert when the SFDs are in tolerance, the correct input signals are received on the VXn digital pins, no warnings are received from any of the inputs of the device, and so on. The PDOs can be used for a variety of functions. The primary function is to provide enable signals for LDOs or dc/dc converters, which generate supplies locally on a board. The PDOs can also be used to provide a POWER_GOOD signal when all the SFDs are in tolerance, or a RESET output if one of the SFDs goes out of specification (this can be used as a status signal for a DSP, FPGA, or other microcontroller). The PDOs can be programmed to pull up to a number of different options. The outputs can be programmed as follows: * Open-drain (allowing the user to connect an external pull-up resistor) * Open-drain with weak pull-up to VDD * Push/pull to VDD * Open-drain with weak pull-up to VPn * Push/pull to VPn * Strong pull-down to GND * Internally charge-pumped high drive (12 V, PDO1-6 only) The last option (available only on PDO1-6) allows the user to directly drive a voltage high enough to fully enhance an external N-FET, which is used to isolate, for example, a card-side voltage from a backplane supply (a PDO can sustain greater than 10.5 V into a 1 A load). The pull-down switches can also be used to drive status LEDs directly. The data driving each of the PDOs can come from one of three sources. The source can be enabled in the PnPDOCFG configuration register (see the AN-698 application note for details). The data sources are * Output from the SE. * Directly from the SMBus. A PDO can be configured so that the SMBus has direct control over it. This enables software control of the PDOs. Therefore, a microcontroller can be used to initiate a software power-up/power-down sequence. * On-Chip Clock. A 100 kHz clock is generated on the device. This clock can be made available on any of the PDOs. It can be used, for example, to clock an external device such as an LED. By default, the PDOs are pulled to GND by a weak (20 k) onchip pull-down resistor. This is also the condition of the PDOs on power-up, until the configuration is downloaded from EEPROM and the programmed setup is latched. The outputs are actively pulled low once a supply of 1 V or greater is on VPn or VH. The outputs remain high impedance prior to 1 V appearing on VPn or VH. This provides a known condition for the PDOs during power-up. The internal pull-down can be overdriven with an external pull-up of suitable value tied from the PDO pin to the required pull-up voltage. The 20 k resistor must be accounted for in calculating a suitable value. For example, if PDOn must be pulled up to 3.3 V, and 5 V is available as an external supply, the pull-up resistor value is given by 3.3 V = 5 V x 20 k/(RUP + 20 k) Therefore, RUP = (100 k - 66 k)/3.3 = 10 k
VFET (PDO1-6 ONLY) VDD VP4 CFG4 CFG5 CFG6 SEL VP1
20k
20k
SE DATA SMBus DATA CLK DATA PDO
20k 20k
10
10
10
Figure 22. Programmable Driver Output
Rev. 0 | Page 16 of 32
04633-028
ADM1064 SEQUENCING ENGINE
OVERVIEW
The ADM1064's sequencing engine (SE) provides the user with powerful and flexible control of sequencing. The SE implements a state machine control of the PDO outputs, with state changes conditional on input events. SE programs can enable complex control of boards such as power-up and power-down sequence control, fault event handling, interrupt generation on warnings, and so on. A watchdog function that verifies the continued operation of a processor clock can be integrated into the SE program. The SE can also be controlled via the SMBus, giving software or firmware control of the board sequencing. The SE state machine comprises 63 state cells. Each state has the following attributes: * Monitors signals indicating the status of the 10 input pins, VP1 to VP4, VH, and VX1 to VX5. * Can be entered from any other state. * Three exit routes move the state machine on to a next state: sequence detection, fault monitoring, and timeout. * Delay timers for the sequence and timeout blocks can be programmed independently, and change with each state change. The range of timeouts is from 0 ms to 400 ms. * Output condition of the 10 PDO pins is defined and fixed within a state. * Transition from one state to the next is made in less than 20 s, which is the time needed to download a state definition from EEPROM to the SE.
MONITOR FAULT
STATE
TIMEOUT
SEQUENCE
Figure 23. State Cell
The ADM1064 offers up to 63 state definitions. The signals monitored to indicate the status of the input pins are the outputs of the SFDs.
WARNINGS
The SE also monitors warnings. These warnings can be generated when the ADC readings violate their limit register value or when the secondary voltage monitors on VP1-4 and VH. The warnings are all OR'ed together and are available as a single warning input to each of the three blocks that enable exiting from a state.
SMBUS JUMP/UNCONDITIONAL JUMP
The SE can be forced to advance to the next state unconditionally. This enables the user to force the SE to advance. Examples of where this might be used include moving to a margining state or debugging a sequence. The SMBus jump or go-to command can be seen as another input to sequence and timeout blocks, which provide an exit from each state.
Table 6. Sample Sequence State Entries
State IDLE1 IDLE2 EN3V3 DIS3V3 EN2V5 DIS2V5 FSEL1 FSEL2 PWRGD Sequence If VX1 is low , go to state IDLE2. If VP1 is okay, go to state EN3V3. If VP2 is okay, go to state EN2V5. If VX1 is high, go to state IDLE1. If VP3 is okay, go to state PWRGD. If VX1 is high, go to state IDLE1. If VP3 is not okay, go to state DIS2V5. If VP2 is not okay, go to state DIS3V3. If VX1 is high, go to state DIS2V5. Timeout Monitor
If VP2 is not okay after 10 ms, go to state DIS3V3. If VP3 is not okay after 20 ms, go to state DIS2V5.
If VP1 is not okay, go to state IDLE1.
If VP1 or VP2 is not okay, go to state FSEL2.
If VP1 or VP2 is not okay, go to state FSEL2. If VP1 is not okay, go to state IDLE1. If VP1, VP2, or VP3 is not okay, go to state FSEL1.
Rev. 0 | Page 17 of 32
04633-029
ADM1064
SEQUENCING ENGINE APPLICATION EXAMPLE
The application in this section demonstrates the operation of the SE. Figure 24 shows how the simple building block of a single SE state can be used to build a power-up sequence for a 3-supply system. Table 7 lists the PDO outputs for each state in the same SE implementation. In this system, the presence of a good 5 V supply on VP1 and the VX1 pin held low are the triggers required for a power-up sequence to start. The sequence intends to turn on the 3.3 V supply next, then the 2.5 V supply (assuming successful turn-on of the 3.3 V supply). Once all three supplies are good, the PWRGD state is entered, where the SE remains until a fault occurs on one of the three supplies, or it is instructed to go through a power-down sequence by VX1 going high. Faults are dealt with throughout the power-up sequence on a case-by-case basis. The following sections, which describe the individual blocks, use this sample application to demonstrate the state machine's actions.
SEQUENCE STATES
IDLE1
VX1 = 0
IDLE2
MONITOR FAULT STATES
VP1 = 1
TIMEOUT STATES
EN3V3
VP1 = 0 10ms
VP2 = 1
EN2V5
(VP1 + VP2) = 0 20ms
DIS3V3
VX1 = 1
VP3 = 1
PWRGD
VP2 = 0 (VP1 + VP2 + VP3) = 0
DIS2V5
VX1 = 1
FSEL1
(VP1 + VP2) = 0 VP3 = 0
VX1 = 1
FSEL2
VP1 = 0 VP2 = 0
04633-030
Figure 24. Sample Application Flow Diagram
Table 7. PDO Outputs for Each State
PDO Outputs PDO1 = 3V3ON PDO2 = 2V5ON PDO3 = FAULT IDLE1 0 0 0 IDLE2 0 0 0 EN3V3 1 0 0 EN2V5 1 1 0 DIS3V3 0 1 1 DIS2V5 1 0 1 PWRGD 1 1 0 FSEL1 1 1 1 FSEL2 1 1 1
Rev. 0 | Page 18 of 32
ADM1064
SEQUENCE DETECTOR
The sequence detector block is used to detect when a step in a sequence has been completed. It looks for one of the inputs to the SE to change state, and is most often used as the gate on successful progress through a power-up or power-down sequence. A timer block is included in this detector, which can insert delays into a power-up or power-down sequence, if required. Timer delays can be set from 10 s to 400 ms. Figure 25 is a block diagram of the sequence detector.
VP1 SUPPLY FAULT DETECTION
MONITORING FAULT DETECTOR 1-BIT FAULT DETECTOR VP1 SUPPLY FAULT DETECTION MASK SENSE FAULT
1-BIT FAULT DETECTOR VX5 LOGIC INPUT CHANGE OR FAULT DETECTION MASK SENSE FAULT
SEQUENCE DETECTOR
VX5
LOGIC INPUT CHANGE OR FAULT DETECTION TIMER
1-BIT FAULT DETECTOR WARNINGS FAULT
WARNINGS INVERT FORCE FLOW (UNCONDITIONAL JUMP)
04633-032
MASK
Figure 26. Monitoring Fault Detector Block Diagram
SELECT
TIMEOUT DETECTOR
The timeout detector allows the user to trap a failure to make proper progress through a power-up or power-down sequence. In the sample application shown in Figure 24, the timeout nextstate transition is from the EN3V3 and EN2V5 states. For the EN3V3 state, the signal 3V3ON is asserted upon entry to this state (on the PDO1 output pin) to turn on a 3.3 V supply. This supply rail is connected to the VP2 pin, and the sequence detector looks for the VP2 pin to go above its UV threshold, which is set in the supply fault detector (SFD) attached to that pin. The power-up sequence progresses when this change is detected. If, however, the supply fails (perhaps due to a short circuit overloading this supply), then the timeout block traps the problem. In this example, if the 3.3 V supply fails within 10 ms, then the SE moves to the DIS3V3 state and turns off this supply by bringing PDO1 low. It also indicates that a fault has occurred by taking PDO3 high. Timeout delays of from 100 s to 400 ms can be programmed.
Figure 25. Sequence Detector Block Diagram
The sequence detector can also help to identify monitoring faults. In the sample application shown in Figure 24, the FSEL1 and FSEL2 states first identify which of the VP1,VP2, or VP3 pins has faulted, and then they take the appropriate action.
MONITORING FAULT DETECTOR
The monitoring fault detector block is used to detect a failure on an input. The logical function implementing this is a wide OR gate, which can detect when an input deviates from its expected condition. The clearest demonstration of the use of this block is in the PWRGD state, where the monitor block indicates that a failure on one or more of the VP1,VP2, or VP3 inputs has occurred. No programmable delay is available in this block, because the triggering of a fault condition is likely to be caused when a supply falls out of tolerance. In this situation, the user would want to react as quickly as possible. Some latency occurs when moving out of this state, however, because it takes a finite amount of time (~20 s) for the state configuration to download from EEPROM into the SE. Figure 26 is a block diagram of the monitoring fault detector.
FAULT REPORTING
The ADM1064 has a fault latch for recording faults. Two registers are set aside for this purpose. A single bit is assigned to each input of the device, and a fault on that input sets the relevant bit. The contents of the fault register can be read out over the SMBus to determine which input(s) faulted. The fault register can be enabled/disabled in each state. This ensures that only real faults are captured and not, for example, undervoltage trips when the SE is executing a power-down sequence.
Rev. 0 | Page 19 of 32
04633-033
ADM1064 VOLTAGE READBACK
The ADM1064 has an on-board 12-bit accurate ADC for voltage readback over the SMBus. The ADC has a 12-channel analog mux on the front end. The twelve channels consist of the ten SFD inputs (VH, VP1-4, VX1-5) and two auxiliary (singleended) ADC inputs (AXU1, AUX2). Any or all of these inputs can be selected to be read, in turn, by the ADC. The circuit controlling this operation is called round-robin. The roundrobin circuit can be selected to run through its loop of conversions just once or continuously. Averaging is also provided for each channel. In this case, the round-robin circuit runs through its loop of conversions 16 times before returning a result for each channel. At the end of this cycle, the results are all written to the output registers. The ADC samples single-sided inputs with respect to the AGND pin. A 0 V input gives out Code 0, and an input equal to the voltage on REFIN gives out full code (4095 decimal). The inputs to the ADC come directly from the VXn pins and from the back of the input attenuators on the VPn and VH pins, as shown in Figure 27 and Figure 28.
NO ATTENUATION VXn 12-BIT ADC
04633-025
Table 8. ADC Input Voltage Ranges
SFD Input Range (V) 0.573-1.375 1.25-3 2.5-6 4.8-14.4
1
Attenuation Factor 1 2.181 4.363 10.472
ADC Input Voltage Range (V) 0-2.048 0-4.46 0-6.01 0-14.41
_______________________________________________
The upper limit is the absolute maximum allowed voltage on these pins.
The normal way to supply the reference to the ADC on the REFIN pin is to simply connect the REFOUT pin to the REFIN pin. REFOUT provides a 2.048 V reference. As such, the supervising range covers less than half of the normal ADC range. It is possible, however, to provide the ADC with a more accurate external reference for improved readback accuracy. Supplies can also be connected to the input pins purely for ADC readback, even though they might go above the expected supervisory range limits (but not above 6 V, because this violates the absolute maximum ratings on these pins). For instance, a 1.5 V supply connected to the VX1 pin can be correctly read out as an ADC code of approximately 3/4 full scale, but it always sits above any supervisory limits that can be set on that pin. The maximum setting for the REFIN pin is 2.048 V.
DIGITIZED VOLTAGE READING
2.048V VREF
SUPPLY SUPERVISION WITH THE ADC
In addition to the readback capability, a further level of supervision is provided by the on-chip 12-bit ADC. The ADM1064 has limit registers on which the user can program to a maximum or minimum allowable threshold. Exceeding the threshold generates a warning that can either be read back from the status registers or input into the SE to determine what sequencing action the ADM1064 should take. Only one register is provided for each input channel, so a UV or OV threshold (but not both) can be set for a given channel. The round-robin circuit can be enabled via an SMBus write, or it can be programmed to turn on in any state in the SE program. For example, it can be set to start once a power-up sequence is complete and all supplies are known to be within expected tolerance limits. Note that a latency is built into this supervision, dictated by the conversion time of the ADC. With all 12 channels selected, the total time for the round-robin operation (averaging off) is approximately 6 ms (500 s per channel selected). Supervision using the ADC, therefore, does not provide the same real time response as the SFDs.
Figure 27. ADC Reading on VXn Pins
VPn/VH
ATTENUATION NETWORK (DEPENDS ON RANGE SELECTED) DIGITIZED VOLTAGE READING 12-BIT ADC
04633-026
2.048V VREF
Figure 28. ADC Reading on VPn/VH Pins
The voltage at the input pin can be derived from the following equation: V=
ADC Code 4095
x Attenuation Factor x 2.048 V
The ADC input voltage ranges for the SFD input ranges are listed in Table 8.
Rev. 0 | Page 20 of 32
ADM1064 APPLICATIONS DIAGRAM
12V IN 5V IN 3V IN IN 12V OUT 5V OUT 3V OUT
DC-DC1
EN VH 5V OUT 3V OUT 3.3V OUT 2.5V OUT 1.8V OUT 1.2V OUT 0.9V OUT POWER_ON VX4 RESET_L VX5 VP1 VP2 VP3 VP4 VX1 VX2 VX3 OUT 3.3V OUT
ADM1064
PDO1 PDO2 IN PDO3 PDO4 PDO5 POWER_GOOD PDO6 SIGNAL_VALID PDO7 SYSTEM RESET PDO8 PDO9 PDO10 EN IN
DC-DC2
EN OUT 2.5V OUT
DC-DC3
OUT 3.3V OUT IN 1.8V OUT
REFIN VCCP VDDCAP GND
LDO
10F 10F 10F 3.3V OUT IN EN
04633-068
EN
OUT
0.9V OUT
OUT
1.2V OUT
DC-DC4
Figure 29. Applications Diagram
Rev. 0 | Page 21 of 32
ADM1064 COMMUNICATING WITH THE ADM1064
CONFIGURATION DOWNLOAD AT POWER-UP
The configuration of the ADM1064 (UV/OV thresholds, glitch filter timeouts, PDO configurations, and so on) is dictated by the contents of RAM. The RAM is comprised of digital latches that are local to each of the functions on the device. The latches are double-buffered and have two identical latches, Latch A and Latch B. Therefore, when an update to a function occurs, the contents of Latch A are updated first, and then the contents of Latch B are updated with identical data. The advantages of this architecture are explained in detail in this section. The latches are volatile memory and lose their contents at power-down. Therefore, the configuration in the RAM must be restored at power-up by downloading the contents of the EEPROM (nonvolatile memory) to the local latches. This download occurs in steps, as follows: 1. 2. With no power applied to the device, the PDOs are all high impedance. When 1 V appears on any of the inputs connected to the VDD arbitrator (VH or VPn), the PDOs are all weakly pulled to GND with a 20 k impedance. When the supply rises above the undervoltage lockout of the device (UVLO is 2.5 V), the EEPROM starts to download to the RAM. The EEPROM downloads its contents to all Latch As. Once the contents of the EEPROM are completely downloaded to the Latch As, the device controller signals all Latch As to download to all Latch Bs simultaneously, completing the configuration download. At 0.5 ms after the configuration download completes, the first state definition is downloaded from EEPROM into the SE. The ADM1064 provides several options that allow the user to update the configuration over the SMBus interface. The following options are controlled in the UPDCFG register: 1. Update the configuration in real time. The user writes to RAM across the SMBus and the configuration is updated immediately. Update the Latch As without updating the Latch Bs. With this method, the configuration of the ADM1064 remains unchanged and continues to operate in the original setup until the instruction is given to update the Latch Bs. Change EEPROM register contents without changing the RAM contents, and then download the revised EEPROM contents to the RAM registers. Again, with this method, the configuration of the ADM1064 remains unchanged and continues to operate in the original setup until the instruction is given to update the RAM.
2.
3.
3.
4. 5.
The instruction to download from the EEPROM in Option 3 is also a useful way to restore the original EEPROM contents, if revisions to the configuration are unsatisfactory. For example, if the user needs to alter an OV threshold, this can be done by updating the RAM register as described in Option 1. However, if the user is not satisfied with the change and wants to revert to the original programmed value, then the device controller can issue a command to download the EEPROM contents to the RAM again, as described in Option 3, restoring the ADM1064 to its original configuration. The topology of the ADM1064 makes this type of operation possible. The local, volatile registers (RAM) are all doublebuffered latches. Setting Bit 0 of the UPDCFG register to 1 leaves the double-buffered latches open at all times. If Bit 0 is set to 0, then, when a RAM write occurs across the SMBus, only the first side of the double-buffered latch is written to. The user must then write a 1 to Bit 1 of the UPDCFG register. This generates a pulse to update all the second latches at once. EEPROM writes occur in a similar way. The final bit in this register can enable or disable EEPROM page erasure. If this bit is set high, the contents of an EEPROM page can all be set to 1. If low, then the contents of a page cannot be erased, even if the command code for page erasure is programmed across the SMBus. The bitmap for the UPDCFG register is shown in the AN-698 application note. A flow chart for download at power-up and subsequent configuration updates is shown in Figure 30.
6.
Note that any attempt to communicate with the device prior to the completion of the download causes the ADM1064 to issue a no acknowledge (NACK).
UPDATING THE CONFIGURATION
After power-up, with all the configuration settings loaded from EEPROM into the RAM registers, the user might need to alter the configuration of functions on the ADM1064, such as changing the UV or OV limit of an SFD, changing the fault output of an SFD, or adjusting the rise time delay of one of the PDOs.
Rev. 0 | Page 22 of 32
ADM1064
SMBus
POWER-UP (VCC > 2.5V)
EEPROM
Figure 30. Configuration Update Flow Diagram
UPDATING THE SEQUENCING ENGINE
Sequencing engine (SE) functions are not updated in the same way as regular configuration latches. The SE has its own dedicated 512-byte EEPROM for storing state definitions, providing 63 individual states with a 64-bit word each (one state is reserved). At power-up, the first state is loaded from the SE EEPROM into the engine itself. When the conditions of this state are met, the next state is loaded from EEPROM into the engine, and so on. The loading of each new state takes approximately 10 s. To alter a state, the required changes must be made directly to EEPROM. RAM for each state does not exist. The relevant alterations must be made to the 64-bit word, which is then uploaded directly to EEPROM.
The major differences between the EEPROM and other registers are * * * An EEPROM location must be blank before it can be written to. If it contains data, it must first be erased. Writing to EEPROM is slower than writing to RAM. Writing to the EEPROM should be restricted, because it has a limited write/cycle life of typically 10,000 write operations due to the usual EEPROM wear-out mechanisms.
INTERNAL REGISTERS
The ADM1064 contains a large number of data registers. The principal registers are the address pointer register and the configuration registers.
The first EEPROM is split into 16 (0 to 15) pages of 32 bytes each. Pages 0 to 6, starting at Address 0xF800, hold the configuration data for the applications on the ADM1064 (the SFDs, PDOs, and so on). These EEPROM addresses are the same as the RAM register addresses, prefixed by F8. Page 7 is reserved. Pages 8 to 15 are for customer use. Data can be downloaded from EEPROM to RAM in one of the following ways: * * At power-up, when Pages 0 to 6 are downloaded. By setting Bit 0 of the UDOWNLD register (0xD8), which performs a user download of Pages 0 to 6.
Address Pointer Register
This register contains the address that selects one of the other internal registers. When writing to the ADM1064, the first byte of data is always a register address, which is written to the address pointer register.
Configuration Registers
These registers provide control and configuration for various operating parameters of the ADM1064.
SERIAL BUS INTERFACE
The ADM1064 is controlled via the serial system management bus (SMBus). The ADM1064 is connected to this bus as a slave device, under the control of a master device. It takes approximately 1 ms after power-up for the ADM1064 to download from its EEPROM. Therefore, access to the ADM1064 is restricted until the download is completed.
EEPROM
The ADM1064 has two 512-byte cells of nonvolatile, electrically erasable, programmable read-only memory (EEPROM), from Register Addresses 0xF800 to 0xFBFF. The EEPROM is used for permanent storage of data that is not lost when the ADM1064 is powered down. One EEPROM cell contains the configuration data of the device; the other contains the state definitions for the SE. Although referred to as read-only memory, the EEPROM can be written to as well as read from via the serial bus in exactly the same way as the other registers.
Identifying the ADM1064 on the SMBus
The ADM1060 has a 7-bit serial bus slave address. The device is powered up with a default serial bus address. The five MSBs of the address are set to 01101; the two LSBs are determined by the logical states of Pins A1 and A0. This allows the connection of four ADM1064s to one SMBus.
Rev. 0 | Page 23 of 32
04633-035
E E P R O M L D
DEVICE CONTROLLER D A T A LATCH A
R A M L D
U P D
LATCH B
FUNCTION (OV THRESHOLD ON VP1)
ADM1064
The device also has several identification registers (read-only), which can be read across the SMBus. Table 9 lists these registers with their values and functions. Table 9. Identification Register Values and Functions
Name MANID REVID MARK1 MARK2 Address 0xF4 0xF5 0xF6 0xF7 Value 0x41 0x00 0x00 0x00 Function Manufacturer ID for Analog Devices Silicon revision S/w brand S/w brand
All other devices on the bus remain idle while the selected device waits for data to be read from or written to it. If the R/W bit is a 0, the master writes to the slave device. If the R/W bit is a 1, the master reads from the slave device. 2. Data is sent over the serial bus in sequences of nine clock pulses, eight bits of data followed by an acknowledge bit from the slave device. Data transitions on the data line must occur during the low period of the clock signal and remain stable during the high period, because a low-tohigh transition when the clock is high might be interpreted as a stop signal. If the operation is a write operation, the first data byte after the slave address is a command byte. This tells the slave device what to expect next. It might be an instruction telling the slave device to expect a block write, or it might simply be a register address that tells the slave where subsequent data is to be written. Because data can flow in only one direction, as defined by the R/W bit, sending a command to a slave device during a read operation is not possible. Before a read operation, it might be necessary to perform a write operation to tell the slave what sort of read operation to expect and/or the address from which data is to be read. When all data bytes have been read or written, stop conditions are established. In write mode, the master pulls the data line high during the 10th clock pulse to assert a stop condition. In read mode, the master device releases the SDA line during the low period before the ninth clock pulse, but the slave device does not pull it low. This is known as no acknowledge. The master then takes the data line low during the low period before the tenth clock pulse, then high during the tenth clock pulse to assert a stop condition.
General SMBus Timing
Figure 31, Figure 32, and Figure 33 are timing diagrams for general read and write operations using the SMBus. The SMBus specification defines specific conditions for different types of read and write operations, which are discussed in the Write Operations and Read Operations sections. The general SMBus protocol operates as follows: 1. The master initiates data transfer by establishing a start condition, defined as a high-to-low transition on the serial data-line SDA, while the serial clock-line SCL remains high. This indicates that a data stream follows. All slave peripherals connected to the serial bus respond to the start condition and shift in the next 8 bits, consisting of a 7-bit slave address (MSB first) plus a R/W bit. This bit determines the direction of the data transfer, that is, whether data is written to or read from the slave device (0 = write, 1 = read). The peripheral whose address corresponds to the transmitted address responds by pulling the data line low during the low period before the ninth clock pulse, known as the acknowledge bit, and holding it low during the high period of this clock pulse.
1 SCL 9 1
3.
9
SDA
0 START BY MASTER
1
1
0
1
A1
A0
R/W ACK. BY SLAVE
D7
D6
D5
D4
D3
D2
D1
D0 ACK. BY SLAVE
FRAME 1 SLAVE ADDRESS 1 SCL (CONTINUED) SDA (CONTINUED) D7 D6 D5 D4 D3 D2 D1 D0 ACK. BY SLAVE D7 9 1
FRAME 2 COMMAND CODE 9
D6
D5
D4
D3
D2
D1
D0
04633-036
FRAME 3 DATA BYTE
FRAME N DATA BYTE
ACK. BY SLAVE
STOP BY MASTER
Figure 31. General SMBus Write Timing Diagram
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ADM1064
1 SCL 9 1 9
SDA
0 START BY MASTER 1
1
1
0
1
A1
A0 R/W ACK. BY SLAVE
D7
D6
D5
D4
D3
D2
D1
D0 ACK. BY MASTER
FRAME 1 SLAVE ADDRESS
9
1
FRAME 2 DATA BYTE
9
SCL (CONTINUED) SDA (CONTINUED) D7 D6 D5 D4 D3 D2 D1 D0 ACK. BY MASTER D7 D6 D5 D4 D3 D2 D1 D0 NO ACK. FRAME N DATA BYTE
04633-037
FRAME 3 DATA BYTE
STOP BY MASTER
Figure 32. General SMBus Read Timing Diagram
tR
SCL
tF
t HD; STA
t LO W t HD; STA t HD; DAT t SU; DAT
04633-038
t HI G H
t SU; STA
t SU; STO
SDA
t BUF
P S S P
Figure 33. Serial Bus Timing Diagram
SMBUS PROTOCOLS FOR RAM AND EEPROM
The ADM1064 contains volatile registers (RAM) and nonvolatile registers (EEPROM). User RAM occupies address locations from 0x00 to 0xDF; EEPROM occupies addresses from 0xF800 to 0xFBFF. Data can be written to and read from both RAM and EEPROM as single data bytes. Data can be written only to unprogrammed EEPROM locations. To write new data to a programmed location, it must first be erased. EEPROM erasure cannot be done at the byte level. The EEPROM is arranged as 32 pages of 32 bytes each, and an entire page must be erased. Page erasure is enabled by setting Bit 2 in the UPDCFG register (Address 0x90) to 1. If this bit is not set, page erasure cannot occur, even if the command byte (0xFE) is programmed across the SMBus. The ADM1064 uses the following SMBus write protocols.
Send Byte
In a send byte operation, the master device sends a single command byte to a slave device, as follows: 1. 2. 3. 4. 5. 6. The master device asserts a start condition on SDA. The master sends the 7-bit slave address followed by the write bit (low). The addressed slave device asserts ACK on SDA. The master sends a command code. The slave asserts ACK on SDA. The master asserts a stop condition on SDA and the transaction ends.
WRITE OPERATIONS
The SMBus specification defines several protocols for different types of read and write operations. The following abbreviations are used in the diagrams:
S P R W A A Start Stop Read Write Acknowledge No acknowledge
In the ADM1064, the send byte protocol is used for two purposes: * To write a register address to RAM for a subsequent single byte read from the same address, or a block read or write starting at that address, as shown in Figure 34.
1 S 2 SLAVE ADDRESS W 3 A 4 REGISTER ADDRESS (0x00 TO 0xDF) 5 A 6 P
04633-039
Figure 34. Setting a RAM Address for Subsequent Read
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ADM1064
* To erase a page of EEPROM memory. EEPROM memory can be written to only if it is unprogrammed. Before writing to one or more EEPROM memory locations that are already programmed, the page or pages containing those locations must first be erased. EEPROM memory is erased by writing a command byte. The master sends a command code that tells the slave device to erase the page. The ADM1064 command code for a page erasure is 0xFE (1111 1110). Note that, for a page erasure to take place, the page address has to be given in the previous write word transaction (see the Write Byte/Word section). Also, Bit 2 in the UPDCFG register (Address 0x90) must be set to 1.
1 S 2 SLAVE ADDRESS W 3 A 4 COMMAND BYTE (0xFE) 5 A 6 P
04633-040
In the ADM1064, the write byte/word protocol is used for three purposes: * To write a single byte of data to RAM. In this case, the command byte is the RAM address from 0x00 to 0xDF and the only data byte is the actual data, as shown in Figure 36.
1 2 3 4 5 6 78
04633-041
RAM S SLAVE W A ADDRESS A ADDRESS (0x00 TO 0xDF)
DATA A P
Figure 36. Single Byte Write to RAM
*
To set up a 2-byte EEPROM address for a subsequent read, write, block read, block write, or page erase. In this case, the command byte is the high byte of the EEPROM address from 0xF8 to 0xFB. The only data byte is the low byte of the EEPROM address, as shown in Figure 37.
1 2 3 4 5 6 78
04633-042
Figure 35. EEPROM Page Erasure
As soon as the ADM1064 receives the command byte, page erasure begins. The master device can send a stop command as soon as it sends the command byte. Page erasure takes approximately 20 ms. If the ADM1064 is accessed before erasure is complete, it responds with a no acknowledge (NACK).
EEPROM EEPROM SLAVE ADDRESS ADDRESS S WA A AP ADDRESS HIGH BYTE LOW BYTE (0xF8 TO 0xFB) (0x00 TO 0xFF)
Figure 37. Setting an EEPROM Address
Write Byte/Word
In a write byte/word operation, the master device sends a command byte and one or two data bytes to the slave device, as follows: 1. 2. 3. 4. 5. 6. 7. 8. 9. The master device asserts a start condition on SDA. The master sends the 7-bit slave address followed by the write bit (low). The addressed slave device asserts ACK on SDA. The master sends a command code. The slave asserts ACK on SDA. The master sends a data byte. The slave asserts ACK on SDA. The master sends a data byte (or asserts a stop condition at this point). The slave asserts ACK on SDA. 2. 10. The master asserts a stop condition on SDA to end the transaction. 3. 4. *
Note, for page erasure, that because a page consists of 32 bytes, only the three MSBs of the address low byte are important. The lower five bits of the EEPROM address low byte specify the addresses within a page and are ignored during an erase operation. To write a single byte of data to EEPROM. In this case, the command byte is the high byte of the EEPROM address from 0xF8 to 0xFB. The first data byte is the low byte of the EEPROM address, and the second data byte is the actual data, as shown in Figure 38.
1 2 3 4 5 6 7 8 9 10
04633-043
EEPROM EEPROM SLAVE ADDRESS ADDRESS S WA A A DATA A P ADDRESS HIGH BYTE LOW BYTE (0xF8 TO 0xFB) (0x00 TO 0xFF)
Figure 38. Single Byte Write to EEPROM
Block Write
In a block write operation, the master device writes a block of data to a slave device. The start address for a block write must have been set previously. In the ADM1064, a send byte operation sets a RAM address, and a write byte/word operation sets an EEPROM address, as follows: 1. The master device asserts a start condition on SDA. The master sends the 7-bit slave address followed by the write bit (low). The addressed slave device asserts ACK on SDA. The master sends a command code that tells the slave device to expect a block write. The ADM1064 command code for a block write is 0xFC (1111 1100).
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ADM1064
5. 6. The slave asserts ACK on SDA. The master sends a data byte that tells the slave device how many data bytes are being sent. The SMBus specification allows a maximum of 32 data bytes in a block write. The slave asserts ACK on SDA. The master sends N data bytes. The slave asserts ACK on SDA after each data byte.
In the ADM1064, the receive byte protocol is used to read a single byte of data from a RAM or EEPROM location whose address has previously been set by a send byte or write byte/word operation, as shown in Figure 40.
1 2 SLAVE ADDRESS R 3 A 4 DATA 5 A 6 P
04633-045
7. 8. 9.
S
Figure 40. Single Byte Read from EEPROM or RAM
Block Read
In a block read operation, the master device reads a block of data from a slave device. The start address for a block read must have been set previously. In the ADM1064, this is done by a send byte operation to set a RAM address, or a write byte/word operation to set an EEPROM address. The block read operation itself consists of a send byte operation that sends a block read command to the slave, immediately followed by a repeated start and a read operation that reads out multiple data bytes, as follows: 1. 2. 3. 4. The master device asserts a start condition on SDA. The master sends the 7-bit slave address followed by the write bit (low). The addressed slave device asserts ACK on SDA. The master sends a command code that tells the slave device to expect a block read. The ADM1064 command code for a block read is 0xFD (1111 1101). The slave asserts ACK on SDA. The master asserts a repeat start condition on SDA. The master sends the 7-bit slave address followed by the read bit (high). The slave asserts ACK on SDA. The ADM1064 sends a byte-count data byte that tells the master how many data bytes to expect. The ADM1064 always returns 32 data bytes (0x20), which is the maximum allowed by the SMBus 1.1 specification.
10. The master asserts a stop condition on SDA to end the transaction.
1 2 3 4 5 6
7
8
9
10
04633-044
S SLAVE W A COMMAND 0xFC A BYTE A DATA A DATA A DATA A P COUNT (BLOCK WRITE) ADDRESS 1 N 2
Figure 39. Block Write to EEPROM or RAM
Unlike some EEPROM devices that limit block writes to within a page boundary, there is no limitation on the start address when performing a block write to EEPROM, except * There must be at least N locations from the start address to the highest EEPROM address (0xFBFF), to avoid writing to invalid addresses. If the addresses cross a page boundary, both pages must be erased before programming.
*
Note that the ADM1064 features a clock extend function for writes to EEPROM. Programming an EEPROM byte takes approximately 250 s, which would limit the SMBus clock for repeated or block write operations. The ADM1064 pulls SCL low and extends the clock pulse when it cannot accept any more data.
5. 6. 7. 8. 9.
READ OPERATIONS
The ADM1064 uses the following SMBus read protocols.
Receive Byte
In a receive byte operation, the master device receives a single byte from a slave device, as follows: 1. 2. 3. 4. 5. 6. The master device asserts a start condition on SDA. The master sends the 7-bit slave address followed by the read bit (high). The addressed slave device asserts ACK on SDA. The master receives a data byte. The master asserts no acknowledge on SDA. The master asserts a stop condition on SDA, and the transaction ends.
10. The master asserts ACK on SDA. 11. The master receives 32 data bytes. 12. The master asserts ACK on SDA after each data byte. 13. The master asserts a stop condition on SDA to end the transaction.
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ADM1064
1 2 3 4 56 7 8 9 10 11 12
2.
S SLAVE W A COMMAND 0xFD A S SLAVE R A BYTE A DATA A ADDRESS (BLOCK READ) ADDRESS COUNT 1
A no acknowledge (NACK) is generated after the PEC byte to signal the end of the read.
13 14 P
04633-046
Note that the PEC byte is calculated using CRC-8. The frame check sequence (FCS) conforms to CRC-8 by the polynomial C(x) = x8 + x2 + x1 + 1 See the SMBus 1.1 specification for details. An example of a block read with the optional PEC byte is shown in Figure 42.
1 2 3 4 56 7 8 9 10 11 12
DATA A 32
Figure 41. Block Read from EEPROM or RAM
Error Correction
The ADM1064 provides the option of issuing a PEC (packet error correction) byte after a write to RAM, a write to EEPROM, a block write to RAM/EEPROM, or a block read from RAM/EEPROM. This enables the user to verify that the data received by or sent from the ADM1064 is correct. The PEC byte is an optional byte sent after that last data byte has been written to or read from the ADM1064. The protocol is as follows: 1. The ADM1064 issues a PEC byte to the master. The master checks the PEC byte and issues another block read, if the PEC byte is incorrect.
S SLAVE W A COMMAND 0xFD A S SLAVE R A BYTE A DATA A ADDRESS (BLOCK READ) ADDRESS COUNT 1
13 14 15 A PEC A P
04633-047
DATA 32
Figure 42. Block Read from EEPROM or RAM with PEC
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ADM1064 OUTLINE DIMENSIONS
6.00 BSC SQ 0.60 MAX
31 30 40 1
0.60 MAX PIN 1 INDICATOR
PIN 1 INDICATOR
TOP VIEW
5.75 BCS SQ
0.50 BSC 0.50 0.40 0.30
EXPOSED PAD
(BOTTO M VIEW)
4.25 4.10 SQ 3.95
10 11
21 20
0.25 MIN 4.50 REF
12 MAX
0.80 MAX 0.65 TYP 0.05 MAX 0.02 NOM
1.00 0.85 0.80
SEATING PLANE
0.30 0.23 0.18
0.20 REF
COPLANARITY 0.08
COMPLIANT TO JEDEC STANDARDS MO-220-VJJD-2
Figure 43. 40-Lead Lead Frame Chip Scale Package [LFCSP] (CP-40) Dimensions shown in millimeters
0.75 0.60 0.45 SEATING PLANE
1.20 MAX
48 1
9.00 BSC SQ
37 36 PIN 1
TOP VIEW
(PINS DOWN)
7.00 BSC SQ
1.05 1.00 0.95
0 MIN
VIEW A
12 13 25 24
0.15 0.05
SEATING PLANE
0.20 0.09 7 3.5 0 0.08 MAX COPLANARITY
0.50 BSC
0.27 0.22 0.17
VIEW A
ROTATED 90 CCW
COMPLIANT TO JEDEC STANDARDS MS-026ABC
Figure 44. 48-Lead Thin Plastic Quad Flat Package [TQFP] (SU-48) Dimensions shown in millimeters
ORDERING GUIDE
Model ADM1064ACP ADM1064ACP-REEL ADM1064ACP-REEL7 ADM1064ASU ADM1064ASU-REEL ADM1064ASU-REEL7 EVAL-ADM1064LFEB EVAL-ADM1064TQEB Temperature Range -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C Package Description 40-Lead LFCSP 40-Lead LFCSP 40-Lead LFCSP 48-Lead TQFP 48-Lead TQFP 48-Lead TQFP ADM1064 Evaluation Kit (LFSCP Version) ADM1064 Evaluation Kit (TQFP Version) Package Option CP-40 CP-40 CP-40 SU-48 SU-48 SU-48
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ADM1064 NOTES
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ADM1064 NOTES
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ADM1064 NOTES
(c) 2004 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D04633-0-10/04(0)
Rev. 0 | Page 32 of 32
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